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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
March 2009
FAN4800A/C, FAN4801/1S/2/2L PFC/PWM Controller Combination
Features
Pin-to-Pin Compatible with ML4800 and FAN4800 and CM6800 and CM6800A PWM Configurable for Current-mode or Feed-forward Voltage-Mode Operation Internally Synchronized Leading-Edge PFC and Trailing-Edge PWM in one IC Low Operating Current Innovative Switching-Charge Multiplier Divider Average-Current-Mode for Input-Current Shaping PFC Over-Voltage and Under-Voltage Protections PFC Feedback Open-Loop Protection Cycle-by-Cycle Current Limiting for PFC/PWM Power-on Sequence Control and Soft-Start Brownout Protection Interleaved PFC/PWM Switching FAN4801/1S/2/2L Improve Efficiency at Light Load fRTCT=4*fPFC=4*fPWM for FAN4800A and FAN4801/1S fRTCT=4*fPFC=2*fPWM for FAN4800C and FAN4802/2L
Description
The highly integrated FAN4800A/C and FAN4801/1S/2/2L are specially designed for power supplies that consist of boost PFC and PWM. They require very few external components to achieve versatile protections / compensation. They are available in 16-pin DIP and SOP packages. The PWM can be used in either current or voltage mode. In voltage mode, feed-forward from the PFC output bus can reduce the secondary output ripple. Compared with older productions, ML4800 and FAN4800, FAN4800A/C and FAN4801/1S/2/2L have lower operation current that save power consumption in external devices. FAN4800A/C and FAN4801/1S/2/2L have accurate 49.9% maximum duty of PWM that makes the hold-up time longer. Specifically, the brownout protection and PFC soft-start functions are not in ML4800 and FAN4800. To start evaluating FAN4800A/C, FAN4801/1S/2/2L for replacing existing FAN4800 and ML4800 boards, five things must be done before the fine-tuning procedure: 1. 2. Change RAC resister from the old value to a higher resister: between 6M to 8M. Change RT/CT pin from the existing values to RT=6.8K and CT=1000pF to have fPFC=64KHz, fPWM=64KHz. VRMS pin needs to be 1.224V at VIN=85 VAC for universal input application from line input from 85VAC to 270 VAC. Both poles for the Vrms of FAN4801/1S/2/2L don't need to substantially slower than FAN4800; about 5 to 10 times. At full load, the average VEA needs to ~4.5V and the ripple on the VEA needs to be less than 400mV. Soft-Start pin, the soft-start current has been reduced to half from the FAN4800 capacitor.
Applications
Desktop PC Power Supply Internet Server Power Supply LCD TV, Monitor Power Supply UPS Battery Charger DC Motor Power Supply Monitor Power Supply Telecom System Power Supply Distributed Power
3.
4. 5.
Related Resources
Complete design instructions are detailed in application note AN-6078SC (available in Chinese only).
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Ordering Information
Part Number
FAN4800ANY FAN4800CNY FAN4800AMY FAN4800CMY FAN4801NY FAN4801SNY FAN4802NY FAN4802LNY FAN4801MY FAN4801SMY FAN4802MY FAN4802LMY
Operating Temperature Range
-40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Eco Status
Green Green Green Green Green Green Green Green Green Green Green Green
Package
16-pin Dual In-Line Package (DIP) 16-pin Dual In-Line Package (DIP) 16-pin Small Out-Line Package (SOP) 16-pin Small Out-Line Package (SOP) 16-pin Dual In-Line Package (DIP) 16-pin Dual In-Line Package (DIP) 16-pin Dual In-Line Package (DIP)) 16-pin Dual In-Line Package (DIP)) 16-pin Small Out-Line Package (SOP) 16-pin Small Out-Line Package (SOP) 16-pin Small Out-Line Package (SOP) 16-pin Small Out-Line Package (SOP)
Packing Method
Tube Tube Tape & Reel Tape & Reel Tube Tube Tube Tube Tape & Reel Tape & Reel Tape & Reel Tape & Reel
For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Part Number
FAN4800ANY FAN4800AMY FAN4800CNY FAN4800CMY FAN4801NY FAN4801SNY FAN4802NY FAN4802LNY FAN4801MY FAN4801SMY FAN4802MY FAN4802LMY
PFC:PWM Frequency Ratio
1:1 1:1 1:2 1:2 1:1 1:1 1:2 1:2 1:1 1:1 1:2 1:2
Brown Out / In
1.05V / 1.90V 1.05V / 1.90V 1.05V / 1.90V 1.05V / 1.90V 1.05V / 1.90V 1.05V / 1.90V 1.05V / 1.90V 0.90V / 1.65V 1.05V / 1.90V 1.05V / 1.90V 1.05V / 1.90V 0.90V / 1.65V
Range In / Out
N.A N.A N.A N.A 1.95V / 2.45V 2.80V / 3.35V 1.95V / 2.45V 1.95V / 2.45V 1.95V / 2.45V 2.80V / 3.35V 1.95V / 2.45V 1.95V / 2.45V
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Application Diagram
IEA IAC ISENSE VRMS SS FBPWM RT/CT RAMP VREF FAN4800A/C FAN4801/1S/2/2L
VEA FBPFC VREF VDD VDD OPFC OPWM GND ILIMIT
Secondary
Figure 1.
Typical Application Current Mode
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Application Diagram
IEA IAC ISENSE VRMS SS FBPWM RT/CT RAMP VREF FAN4800A/C FAN4801/1S/2/2L VREF
VEA FBPFC VREF VDD VDD OPFC OPWM GND ILIMIT
Secondary
Figure 2.
Typical Application Voltage Mode
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Block Diagram
Figure 3. FAN4800A/C Function Block Diagram
Figure 4. FAN4801/1S/2/2L Function Block Diagram
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1 www.fairchildsemi.com 5
FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Marking Information
F - Fairchild logo Z - Plant code X - 1 digit year code Y - 1 digit week code TT - 2 digits die run code T - Package type (N:DIP, M:SOP) P - Y: Green package M - Manufacture flow code
Figure 5. Top Mark
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Pin Configuration
Figure 6. Pin Configuration (Top View)
Pin Definitions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Name
IEA IAC ISENSE VRMS SS FBPWM RT/CT RAMP ILIMIT GND OPWM OPFC VDD VREF FBPFC VEA
Description
Output of PFC Current Amplifier. The signal from this pin is compared with an internal sawtooth to determine the pulse width for PFC gate drive. Input AC Current. For normal operation, this input provides current reference for the multiplier. The suggested maximum IAC is 100A. PFC Current Sense. The non-inverting input of the PFC current amplifier and the output of multiplier and PFC ILIMIT comparator. Line-Voltage Detection. Line voltage detection. The pin is used for PFC multiplier. PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10A constant current source. The voltage on FBPWM is clamped by SS during startup. In the event of a protection condition occurring and/or PWM disabled, the SS pin is quickly discharged. PWM Feedback Input. The control input for voltage-loop feedback of PWM stage. Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT. PWM RAMP Input. In current mode, this pin functions as the current sense input; when in voltage mode, it is the feed forward sense input from PFC output 380V (feedforward ramp). Peak Current Limit Setting for PWM. The peak current limits setting for PWM. Ground. PWM Gate Drive. The totem-pole output drive for PWM MOSFET. This pin is internally clamped under 15V to protect the MOSFET. PFC Gate Drive. The totem pole output drive for PWM MOSFET. This pin is internally clamped under 15V to protect the MOSFET. Supply. The power supply pin. The threshold voltages for startup and turn-off are 11V and 9.3V, respectively. The operating current is lower than 10mA. Reference Voltage. Buffered output for the internal 7.5V reference. Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop. A compensation network is connected between this pin and ground.
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD VH VL VVREF VIEA VN IAC IREF IPFC-OUT IPWM-OUT PD R j-a TJ TSTG TL ESD
Parameter
DC Supply Voltage SS, FBPWM, RAMP, OPWM, OPFC IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA VREF IEA ISENSE Input AC Current VREF Output Current Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink Power Dissipation TA < 50C Thermal Resistance (Junction to Air) Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering) Electrostatic Discharge Capability Human Body Model Charged Device Model DIP SOP
Min.
-0.3 -0.3 0 -5.0
Max.
30 30.0 7.0 7.5 VVREF+0.3 0.7 1 5 0.5 0.5 800 80.80 104.10
Unit
V V V V V V mA mA A A mW C/W C/W C C C kV V
-40 -55
+125 +150 +260 4.5 1000
Notes: 1. All voltage values, except differential voltage, are given with respect to GND pin. 2. Stresses beyond those listed under "absolute maximum ratings "may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Min.
-40
Typ.
Max.
+105
Unit
C
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Electrical Characteristics
VDD=15V, TA=25C, RT=6.8k, CT=1000pF unless noted operating specifications.
Symbol
VDD Section IDD ST IDD-OP VTH-ON VTH VDD-OVP VDD-OVP Oscillator fOSC-RT/CT fOSC fDV fDT fTV fRV IDischarge fRANGE tPFCD VREF VVREF VVREF1 VVREF2 VVREF-DT
(1)
Parameter
Startup Current Operating Current Turn-on Threshold Voltage Hysteresis VDD OVP VDD OVP Hysteresis RT/CT Frequency PFC & PWM Frequency FAN4800C,FAN4802/02L PWM Frequency Voltage Stability Temperature Stability Total Variation (PFC & (1) PWM) Ramp Voltage
(1)
Conditions
VDD=VTH-ON-0.1V; OPFC OPWM Open VDD=13V; OPFC OPWM Open
Min.
Typ.
30
Max.
80 5.0 12 1.9
Units
A mA V V V V
2.0 10 1.5 27
2.6 11
28 1
29
RT=6.8k, CT=1000pF RT=6.8k, CT=1000pF 11V VDD 22V -40C ~ +105C Line, Temperature Valley to Peak VRAMP=0V, VRT/CT=2.5V RT=6.8k, CT=1000pF IREF=0mA, CREF=0.1F CREF=0.1F, IREF=0mA to 3.5mA VVDD=14V, Rise/Fall Time > 20s CREF=0.1F, VVDD=11V to 22V -40C ~ +105C Line, Load, Temp TJ=125C, 0 ~ 1000HRs VVREF > 7.35V
240 60 120
256 64 128
268 67 134 2 2
kHz kHz % % kHz V
58 2.8 6.5 50 400 7.4 600 7.5 30
70
Discharge Current Frequency Range PFC Dead Time Reference Voltage Load Regulation of Reference Voltage Line Regulation of Reference Voltage Temperature Stability Total Variation Long-Term Stability Maximum Current Output Short Circuit Over-Voltage Protection PFC OVP Hysteresis VEA Voltage OFF OPFC Voltage Level on FBPFC to Enable OPWM During Startup Hysteresis
(1)
15.0 75 800 7.6 50 25 0.4 0.5 7.65 25 25
mA kHz ns V mV mV % V mV mA mA
(1) VVREF-TV (1) VVREF-LS
7.35 5 5
IREF-MAX.
(1) IOS
PFC OVP Comparator VPFC-OVP VPFC-OVP VEAOFF 2.70 200 0.2 2.75 250 0.3 2.80 300 0.4 V mV V
Low-Power Detect Comparator VIN OK Comparator VRD-FBPFC VRD-FBPFC 2.3 1.15 2.4 1.25 2.5 1.35 V V
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Electrical Characteristics (Continued)
VDD=15V, TA=25C, RT=6.8k, CT=1000pF unless noted operating specifications.
Symbol
FBPFC Vref AV Gmv IFBPFC-L IFBPFC-H IBS VVEA-H VVEA-L
Parameter
Input Voltage Range Reference Voltage Open-Loop Gain
(1) (1)
Conditions
Min.
0
Typ.
Max.
6
Units
V V dB mho A A A V
Voltage Error Amplifier at T=25C VNONINV=VINV, VVEA=3.75V at T=25C VFBPFC=2V, VVEA=1.5V VFBPFC=3V, VVEA=6V -1 5.8 6 0.1 0.4 2.45 35 50 40 2.50 42 70 50 -50 -40 1 90 2.55
Transconductance Maximum Source Current Maximum Sink Current Input Bias Current Output High Voltage on VVEA Output Low Voltage on VVEA Input Voltage Range (1) (ISENSE pin) Transconductance Input Offset Voltage Output High Voltage Output Low Voltage Source Current Sink Current Open-Loop Gain
(1)
V
Current Error Amplifier VISENSE GmI VOFFSET VIEA-H VIEA-L IL IH AI -1.5 VNONINV=VINV, VIEA=3.75V VVEA=0V, IAC Open 78 -10 6.8 VISENSE=-0.6V, VIEA=1.5V VISENSE=+0.6V, VIEA=4.0V 40 VFBPFC=VPFC-UVP to FBPFC OPEN, 470pF from FBPFC to GND 0.4 35 7.4 0.1 50 -50 50 -35 88 0.7 100 10 8.0 0.4 V mho mV V V A A dB
Tri-Fault Detect tFBPFC_OPEN VPFC-UVP Time to FBPFC Open
(1)
2 0.5
4 0.6
ms V
PFC Feedback UnderVoltage Protection Input for AC Current
(1)
Gain Modulator IAC Multiplier Linear Range IAC=17.67A, VRMS=1.080V VFBPFC=2.25V, at T=25C IAC=20A, VRMS=1.224V VFBPFC=2.25V, at T=25C GAIN GAIN Modulator
(2)
0 7.50 6.30 3.80 0.95 0.66 9.00 7.00 4.20 1.05 0.73 2 0.74 0.82
100 10.50 7.70 4.60 1.16 0.80
A
IAC=25.69A, VRMS=1.585V VFBPFC=2.25V, at T=25C IAC=51.62A, VRMS=3.169V VFBPFC=2.25V, at T=25C IAC=62.23A, VRMS=3.803V VFBPFC=2.25V, at T=25C
BW Vo(gm)
Bandwidth
(1)
IAC=40A IAC=20A, VRMS=1.224V VFBPFC=2.25V, at T=25C
kHz 0.90 V
Output Voltage=5.7k x (1) (ISENSE-IOFFSET)
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Electrical Characteristics (Continued)
VDD=15V, TA=25C, RT=6.8k, CT=1000pF unless noted operating specifications.
Symbol
Parameter
Peak Current Limit Threshold Voltage, Cycle-by-Cycle Limit PFC ILIMIT-Gain Modulator Output Gate Output Clamping Voltage Gate Low Voltage Gate High Voltage Gate Rising Time Gate Falling Time Maximum Duty Cycle Minimum Duty Cycle
Conditions
Min.
Typ.
Max.
Units
PFC ILIMIT Comparator VPFC-ILIMIT Vpk -1.25 IAC=17.67A, VRMS=1.08V VFBPFC=2.25V, at T=25C 200 -1.15 -1.05 V mV
PFC Output Driver VGATE-CLAMP VGATE-L VGATE-H tr tf DPFC-MAX DPFC-MIN Brown Out VRMS-UVP VRMS-UVP VRMS-UVP tUVP Soft Start VSS-MAX ISS VPWM-ILIMIT tPD tPWM-Bnk Maximum Voltage Soft-Start Current Threshold Voltage Delay to Output Leading-Edge Blanking Time RMS AC Voltage Low RMS AC Voltage High VEA Low VEA Low (FAN4801S) VEA High VEA High (FAN4801S) Two-Level Current When VRMS=1.95V at132Vrms When VRMS=2.45V at150Vrms When VVEA=1.95V at 30% Loading, When VVEA=2.80V at 60% Loading When VVEA=2.45V at 40% Loading, When VVEA=3.35V at 70% Loading FBPFC Two-Level Current 170 0.95 VDD=15V 9.5 10.0 10 1.00 250 250 350 1.05 10.5 V A V ns ns VRMS Threshold Low VRMS Threshold High Hysteresis Under-Voltage Protection Delay Time FAN4800A/C, FAN4801/1S/2 FAN4802L FAN4800A/C, FAN4801/1S/2 FAN4802L FAN4800A/C, FAN4801/1S/2 FAN4802L 1.00 0.85 1.85 1.60 750 650 340 1.05 0.90 1.90 1.65 850 750 410 1.10 0.95 1.95 1.70 950 850 480 V V V V mV mV ms VDD=22V VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=4.7nF; O/P=2V to 9V VDD=15V; CL=4.7nF; O/P=9V to 2V VIEA<1.2V VIEA>4.5V 8 40 40 94 70 60 97 0 120 110 13 15 17 1.5 V V V ns ns % %
PWM ILIMIT Comparator
Range (FAN4801/1S/2/2L) VRMS-L VRMS-H VEA-L 1.90 2.40 1.90 2.75 2.40 3.30 18 1.95 2.45 1.95 2.80 2.45 3.35 20 2.00 2.50 2.00 2.85 2.50 3.40 22 V V V
VEA-H Itc
V A
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Electrical Characteristics (Continued)
VDD=15V, TA=25C, RT=6.8k, CT=1000pF unless noted operating specifications.
Symbol
PWM Output Driver VGATE-CLAMP VGATE-L VGATE-H tr tf DPWM-MAX VPWM-LS
Parameter
Gate Output Clamping Voltage VDD=22V Gate Low Voltage Gate High Voltage Gate Rising Time Gate Falling Time Maximum Duty Cycle PWM Comparator Level Shift
Conditions
Min.
13 8 30 30 49.0 1.3
Typ.
15
Max.
17 1.5
Units
V V V ns ns % V
VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=4.7nF VDD=15V; CL=4.7nF 60 50 49.5 1.5
120 110 50.0 1.8
Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 2 -1 -1 4. Gain=K x 5.3 x (VRMS ) ; K=( ISENSE IOFFSET) x [IAC x (VEA 0.7V)] ; VEA (MAX.)=5.6V.
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Typical Characteristics
20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
2.96 2.94 2.92 2.90
IDD-OP(uA)
IDD-ST(uA)
2.88 2.86 2.84 2.82 2.80 2.78 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 7. IDD-ST vs. Temperature
11.4 11.3 11.2 VTH-ON (V) 11.1
Figure 8. IDD-OP vs. Temperature
2.0 1.9 1.8 VTH(V) 1.7 1.6 1.5 1.4 1.3
11.0 10.9 10.8 -40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Figure 9. VTH-ON vs. Temperature
28.04 28.02 28.00
Figure 10. VTH vs. Temperature
65.0 64.9 64.8
VDD-OVP(V)
27.98 27.96 27.94 27.92 27.90 27.88 27.86 -40 -25 -10 5 20 35 50 65 80 95 110 125
FOSC-FAN4801/1S(kHz)
64.7 64.6 64.5 64.4 64.3 64.2 -40
-25
-10
5
20
35
50
65
80
95
110 125
Figure 11. VDD-OVP vs. Temperature
130.0 129.8 129.6
Figure 12. fOSC-FAN4801/1S vs. Temperature
655 650 645
FOSC-FAN4802/2L(kHz)
129.2 129.0 128.8 128.6 128.4 -40 -25 -10 5 20 35 50 65 80 95 110 125
tPFCD(ns)
129.4
640 635 630 625 620 615 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 13. fOSC-FAN4802/2L vs. Temperature
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Figure 14. tPFCD vs. Temperature
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Typical Characteristics
7.520 7.515 7.510 5 4 3 2 1 0 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 6
7.500 7.495 7.490 7.485 7.480 7.475 -40 -25 -10
VVREF1(mV)
7.505
VVREF(V)
Figure 15. VVREF vs. Temperature
0.20 0.18 0.16 0.14
Figure 16. VVREF1 vs. Temperature
21.5 21.0 20.5
VVREF2(mV)
0.12 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -40 -25 -10 5 20 35 50 65 80 95 110 125
IREF-MAX.(mA)
20.0 19.5 19.0 18.5 18.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 17. VVREF2 vs. Temperature
2.742 2.740 2.738 2.736 2.734 2.732 2.730 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 18. IREF-MAX. vs. Temperature
252.2 252.0
VPFC-OVP(mV)
251.8 251.6 251.4 251.2 251.0 250.8 -40 -25 -10 5 20 35 50 65 80 95 110 125
VPFC-OVP(V)
Figure 19. VPFC-OVP vs. Temperature
2.400 2.398 2.396 2.394 2.392 2.390 2.388 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 20. VPFC-OVP vs. Temperature
1.275 1.270 1.265 1.260 1.255 1.250 1.245 1.240 -40 -25 -10 5 20 35 50 65 80 95 110 125
VRD-FBPFC(V)
VRD-FBPFC(V)
Figure 21. VRD-FBPFC vs. Temperature
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Figure 22. VRD-FBPFC vs. Temperature
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Typical Characteristics
2.502 2.500
73 74
2.498
Gmv(umho)
5 20 35 50 65 80 95 110 125
Vref(V)
2.496 2.494 2.492 2.490 2.488 -40 -25 -10
73
72
72
71 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 23. Vref vs. Temperature
4.5 4.0 3.5 94 92 90
Figure 24. GmV vs. Temperature
VOFFSET(mV)
Gm I(umho)
5 20 35 50 65 80 95 110 125
3.0 2.5 2.0 1.5 1.0 0.5 0.0 -40 -25 -10
88 86 84 82 80 78 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 25. VOFFSET vs. Temperature
7.10 7.05 7.00 6.1 6.0 5.9
Figure 26. GmI vs. Temperature
Rmul(k)
6.95
GAIN2
5.8 5.7 5.6 5.5 5.4
6.90 6.85 6.80 6.75 6.70 -40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Figure 27. GAIN2 vs. Temperature
-1.1775 -1.1780 -1.1785 -1.1790
Figure 28. Rmul vs. Temperature
295 290 285 280
VPFC-ILIMIT(V)
-1.1795 -1.1800 -1.1805 -1.1810 -1.1815 -1.1820 -1.1825
Vpk(mV)
275 270 265 260 255 250
-40 -25 -10
5
20 35 50
65 80 95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Figure 29. VPFC-ILIMIT vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1 15
Figure 30. Vpk vs. Temperature
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Typical Characteristics
1.010 1.009 1.008 10.1 10.0 9.9 9.8
VPWM-ILIMIT (V)
1.007 1.006 1.005 1.004 1.003 1.002 -40 -25 -10 5 20 35 50 65 80 95 110 125
ISS(uA)
9.7 9.6 9.5 9.4 9.3 9.2 9.1 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 31. VPWM-ILIMIT vs. Temperature
1.048 1.047 1.046 867.5 867.0 866.5
Figure 32. ISS vs. Temperature
VRMS-UVP(mV)
1.045
866.0 865.5 865.0 864.5 864.0 863.5 863.0 862.5 862.0
VRMS-UVP(V)
1.044 1.043 1.042 1.041 1.040 1.039 1.038 -40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Figure 33. VRMS-UVP vs. Temperature
1.940 1.939 1.938
Figure 34. VRMS-UVP vs. Temperature
2.446 2.445 2.444 2.443
VRMS-L(V)
1.937 1.936 1.935 1.934 1.933 1.932 1.931 -40 -25 -10 5 20 35 50 65 80 95 110 125
VRMS-H(V)
2.442 2.441 2.440 2.439 2.438 2.437 2.436 2.435 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 35. VRMS-L vs. Temperature
1.942 1.940 1.938
Figure 36. VRMS-H vs. Temperature
2.436 2.434 2.432
VEA-L(V)
1.936 1.934 1.932
VEA-H(V)
2.430 2.428 2.426
1.930
2.424
1.928 -40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95
110
125
Figure 37. VEA-L vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1 16
Figure 38. VEA-H vs. Temperature
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Typical Characteristics
14.7 14.6 14.4 14.3
VGATE-CLAMP-PFC(V)
14.4 14.3 14.2 14.1 14.0 13.9 -40 -25 -10 5 20 35 50 65 80 95 110 125
VGATE-CLAMP-PWM(V)
14.5
14.2 14.1 14.0 13.9 13.8 13.7 13.6 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 39. VGATE-CLAMP-PFC vs. Temperature
96.06 96.04 96.02
Figure 40. VGATE-CLAMP-PWM vs. Temperature
49.80 49.75
DPWM-MAX(%)
DPFC-MAX(%)
96.00 95.98 95.96 95.94 95.92 95.90 95.88 -40 -25 -10 5 20 35 50 65 80 95 110 125
49.70 49.65 49.60 49.55 49.50 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 41. DPFC-MAX vs. Temperature
21.0 20.8 20.6 20.4
Figure 42. DPWM-MAX vs. Temperature
1.460 1.455 1.450 1.445 1.440 1.435 1.430
20.2 20.0 19.8 19.6 19.4 -40 -25 -10 5 20 35 50 65 80 95 110 125
VPWM-LS(V)
Itc(uA)
-40 -25 -10
5
20
35
50
65
80
95 110 125
Figure 43. Itc vs. Temperature
Figure 44. VPWM-LS vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Functional Description
The FAN4800A/C and FAN4801/1S/2/2L consist of an average current controlled, continuous boost Power Factor Correction (PFC) front-end and a synchronized Pulse Width Modulator (PWM) back-end. The PWM can be used in current or voltage mode. In voltage mode, feed forward from the PFC output bus can be used to improve the line regulation of PWM. In either mode, the PWM stage uses conventional trailing-edge, duty-cycle modulation. This patented leading/trailing edge modulation results in a higher usable PFC error amplifier bandwidth and can significantly reduce the size of the PFC DC bus capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the FAN4800A, FAN4801/1S operates at the same frequency as the PFC; and FAN4800C, FAN4802/2L operates at double with PFC. In addition to power factor correction, a number of protection features are built into this series. They include soft-start, PFC over-voltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout (UVLO).
IGAINMOD =
IAC x (VEA - 0.7) VRMS 2
xK
(1)
Note that the output current of the gain modulator is limited around 159A and the maximum output voltage of the gain modulator is limited to 159A x 5.7K=0.906V. This 0.906V also determines the maximum input power. However, IGAINMOD cannot be measured directly from ISENSE. ISENSE=IGAINMOD - IOFFSET and IOFFSET can only be measured when VEA is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 31A ~ 48A.
Selecting RAC for IAC Pin
The IAC pin is the input of the gain modulator and also a current mirror input and requires current input. Selecting a proper resistor RAC provides a good sine wave current derived from the line voltage and helps program the maximum input power and minimum input line voltage. RAC=VIN peak x 56K. For example, if the minimum line voltage is 75VAC, the RAC=75 x 1.414 x 56K=6M.
Gain Modulator
The gain modulator is the heart of the PFC, as the circuit block controls the response of the current loop to line voltage waveform and frequency, RMS line voltage, and PFC output voltages. There are three inputs to the gain modulator: 1. A current representing the instantaneous input voltage (amplitude and wave shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, required in high-power, switching-power conversion environments. The gain modulator responds linearly to this current. 2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to VRMS (except at unusually low values of VRMS, where special gain contouring takes over to limit power dissipation of the circuit components under brownout conditions). 3. The output of the voltage error amplifier, VEA. The gain modulator responds linearly to variations in this voltage. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual ground (negative) input of the current error amplifier. In this way, the gain modulator forms the reference for the current error loop and ultimately controls the instantaneous current draw of the PFC from the power line. The general form of the output of the gain modulator is:
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1 18
Current Amplifier Error, IEA
The current error amplifier's output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current, which results in a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. The inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator causes the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle decreases to achieve a less negative voltage on the ISENSE pin.
PFC Cycle-By-Cycle Current Limiter
As well as being a part of the current feedback loop, the ISENSE pin is a direct input to the cycle-by-cycle current limiter for the PFC section. If the input voltage at this pin is less than -1.15V, the output of the PFC is disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle.
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
TriFault DetectTM
To improve power supply reliability, reduce system component count, and simplify compliance to UL 1950 safety standards, the FAN4800A/C, FAN4801/1S/2/2L includes TriFault Detect. This feature monitors FBPFC for certain PFC fault conditions. In a feedback path failure, the output of the PFC could exceed safe operating limits. With such a failure, FBPFC exceeds its normal operating area. Should FBPFC go too low, too high, or open, TriFault Detect senses the error and terminates the PFC output drive. TriFault detect is an entirely internal circuit. It requires no external components to serve its protective function.
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a negative resistor because an increase in the input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 45 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current-loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: As the reference voltage increases from 0V, it creates a differentiated voltage on IEA, which prevents the PFC from immediately demanding a full duty cycle on its boost converter. Complete design is referred in application note AN-6078SC. There is an RC filter between Rsense and ISENSE pin. There are two reasons to add a filter at the ISENSE pin: 1. Protection: During startup or inrush current conditions, there is a large voltage across Rsense, which is the sensing resistor of the PFC boost converter. It requires the ISENSE filter to attenuate the energy. 2. To reduce L, the boost inductor: The ISENSE filter also can reduce the boost inductor value since the ISENSE filter behaves like an integrator before the ISENSE pin, which is the input of the current error amplifier, IEA. The ISENSE filter is an RC filter. The resistor value of the ISENSE filter is between 100 and 50 because IOFFSET x RFILTER can generate a negative offset voltage of IEA. Selecting an RFILTER equal to 50 keeps the offset of the IEA less than 3mV. Design the pole of ISENSE filter at fPFC/6, one sixth of the PFC switching frequency, so the boost inductor can be reduced six times without disturbing the stability. The capacitor of the ISENSE filter, CFILTER, is approximately 100nF.
PFC Over-Voltage Protection
In the FAN4800A/C, FAN4801/1S/2/2L, the PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load changes suddenly. A resistor divider from the highvoltage DC output of the PFC is fed to FBPFC. When the voltage on FBPFC exceeds 2.75V, the PFC output driver is shut down. The PWM section continues to operate. The OVP comparator has 250mV of hysteresis and the PFC does not restart until the voltage at FBPFC drops below 2.50V. VDD OVP can also serve as a redundant PFC OVP protection. VDD OVP threshold is 28V with 1V hysteresis.
Selecting PFC Rsense
Rsense is the sensing resistor of the PFC boost converter. During the steady state, line input current x Rsense equals IGAINMOD x 5.7K. At full load, the average VEA needs to around 4.5V and ripple on the VEA needs to be less than 400mV. Choose the resistance of the sensing resistor:
Rsense =
( 4.5 - 0.7 ) x 5.7K x IAC x Gain x VIN x 2 x ( 5.6 - 0.7 ) x Line input Power
2
(2)
where 5.6 is VEA maximum output.
PFC Soft-Start
PFC startup is controlled by VEA level. Before FBPFC voltage reaches 2.4V, the VEA level is around 2.8V. At 90VAC, the PFC soft-start time is 90ms.
PFC Brownout
The AC UVP comparator monitors the AC input voltage. The FAN4800A/C, FAN4801/1S/2 disables PFC as lower AC input that the VRMS is less than 1.05V. The brownout voltage of FAN4802L is lower than FAN4801/1S/2 that the VRMS is less than 0.9V.
Figure 45. Compensation Network Connection for the Voltage and Current Error Amplifiers
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Two-Level PFC Function
To improve the efficiency, the system can reduce PFC switching loss at low line and light load by reducing the PFC output voltage. The two-level PFC output of FAN4801/1S/2/2L can be programmable. As Figure 46 shows, FAN4801/1S/2/2L detect VEA pin and VRMS pin to determine the system operates low line and light load or not. At the second-level PFC, there is a current of 20A through RF2 from FBPFC pin. So the second-level PFC output voltage can be calculated as. RF 1 + RF 2 x (2.5V - 20uA x RF 2 ) (3) RF 2 For example, if the second-level PFC output voltage is expected as 300V and normal voltage is 387V, according to the equation, RF2 is 28k RF1 is 4.3M. Output The programmable range of second level PFC output voltage is 340V ~ 300V.
Pulse Width Modulator (PWM)
The operation of the PWM section is straightforward, but there are several points that should be noted. Foremost among these is the inherent synchronization of PWM with the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage-mode operation. In currentmode applications, the PWM ramp (RAMP) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage. It is thereby representative of the current flowing in the converter's output stage. ILIMIT, which provides cycle-bycycle current limiting, is typically connected to RAMP in such applications. For voltage-mode operation and certain specialized applications, RAMP can be connected to a separate RC timing network to generate a voltage ramp against which FBPWM is compared. Under these conditions, the use of voltage feed-forward from the PFC bus can assist in line regulation accuracy and response. As in current-mode operation, the ILIMIT input is used for output stage over-current protection. No voltage error amplifier is included in the PWM stage, as this function is generally performed on the output side of the PWM's isolation boundary. To facilitate the design of opto-coupler feedback circuitry, an offset has been built into the PWM's RAMP input that allows FBPWM to command a 0% duty cycle for input voltages below typical 1.5V.
PWM Cycle-By-Cycle Current Limiter
The ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. When the ILIMIT triggers the cycle-by-cycle bi-cycle current, it limits the PWM duty cycle mode and the power dissipation is reduced during the dead-short condition.
Figure 46. Two-Level PFC Scheme
Oscillator (RT/CT)
The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: 1 fRT / CT = (4) tRT / CT + tDEAD The dead time of the oscillator is derived from the following equation:
VREF - 1 tRT / CT = CT x RT x ln VREF - 3.8 at VREF=7.5V and tRT/CT=CT x RT x 0.56.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if the voltage on FBPFC is less than its nominal 2.4V. Once the voltage reaches 2.4V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins.
(5)
PWM Soft-Start (SS)
PWM startup is controlled by selection of the external capacitor at soft-start. A current source of 10A supplies the charging current for the capacitor and startup of the PWM begins at 1.5V.
The dead time of the oscillator is determined using:
2.8V x CT = 360 x CT (6) 7.78mA The dead time is so small (tRT/CT>>tDEAD) that the operating frequency can typically be approximated by: tDEAD =
fRT / CT =
1 tRT / CT
(7)
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
PWM Control (RAMP)
When the PWM section is used in current mode, RAMP is generally used as the sampling point for a voltage, representing the current in the primary of the PWM's output transformer. The voltage is derived either from a current sensing resistor or a current transformer. In voltage mode, RAMP is the input for a ramp voltage generated by a second set of timing components (RRAMP, CRAMP) that have a minimum value of 0V and a peak value of approximately 6V. In voltage mode, feed forward from the PFC output bus is an excellent way to derive the timing ramp for the PWM stage.
Leading/Trailing Modulation
Conventional PWM techniques employ trailing-edge modulation, in which the switch turns on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing edge modulation is determined during the on-time of the switch. In the case of leading-edge modulation, the switch is turned off exactly at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch is turned on. The effective duty-cycle of the leading-edge modulation is determined during off-time of the switch.
Generating VDD
After turning on the FAN4800A/C, FAN4801/1S/2/2L at 11V, the operating voltage can vary from 9.3V to 28V. The threshold voltage of the VDD OVP comparator is 28V and its hysteresis is 1V. When VDD reaches 28V, OPFC is LOW, and the PWM section is not disturbed. There are two ways to generate VDD: use auxiliary power supply around 15V or use bootstrap winding to self-bias the FAN4800A/C, FAN4801/1S/2/2L system. The bootstrap winding can be taped from the PFC boost choke or the transformer of the DC-to-DC stage.
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Physical Dimensions
16
19.68 18.66
A
9
6.60 6.09
1
8
(0.40)
TOP VIEW
0.38 MIN 5.33 MAX 3.42 3.17 3.81 2.92 2.54 0.58 A 0.35 1.78 1.14 17.78
SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16EREV1
Figure 47. 16-pin Dual In-Line Package (DIP)
8.13 7.62
0.35 0.20 8.69
15 0
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
Physical Dimensions (Continued)
Figure 48. 16-Pin Small Outline Package (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1 www.fairchildsemi.com 23
FAN4800A/C, FAN4801/1S/2/2L -- PFC/PWM Controller Combination
(c) 2008 Fairchild Semiconductor Corporation FAN4800A/C, FAN4801/1S/2/2L * Rev. 1.0.1
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